1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device having a fuse circuit.
2. Description of the Related Art
In general, as a semiconductor device including a Double Data Rate Synchronous DRAM (DDR SDRAM) becomes highly integrated, a large number of memory cells are included in one semiconductor device. If one of these memory cells fails to operate correctly, the semiconductor device may not perform a requested operation.
However, as a fabrication process technology of the semiconductor device has been developed, its operation error occurs in small number of memory cells. If a product yield is considered, it is not efficient to discard the semiconductor device due to small number of memory cells having an operation error.
In order to resolve above concern, a redundant memory cell is further installed on the semiconductor device having a normal memory cell. If the normal memory cell has an error operation, the normal memory cell is replaced with the redundant memory cell. Hereinafter, a memory cell that is replaced with the redundant memory cell is referred to as “a memory cell for repair”.
Here, information, which indicate the replacement of the memory cell for repair with the redundant memory cell, is provided by a redundancy circuit. The redundancy circuit includes a plurality of fuse circuits having a programmed address information (hereinafter, referred to as “a repair address”) of the memory cell for repair. Thus, the redundant memory cell instead of the memory cell for repair is accessed using a repair information signal generated from the redundancy circuit during a read operation or a write operation.
Meanwhile, a programming of a plurality of fuse circuits included in the redundancy circuit is performed using an electrical cutting method or a laser cutting process. The electrical cutting process is performed by applying an over-current to a fuse circuit to be cut. The laser cutting method is performed by blowing a fuse circuit to be cut using a laser beam. The laser cutting method is widely used in the programming of the fuse circuits because the laser cutting method is simpler than the electrical cutting method.
FIG. 1 is a block diagram illustrating a conventional redundancy circuit for a column repair.
A redundancy circuit includes a first to Nth fuse circuits 31_1 to 31_N and a column repair decision circuit 36. A number of fuse circuits may be designed based on a number of column addresses ADDR<1:N> received from an exterior. For example, if the number of column addresses ADDR<1:N> received from the exterior includes N bits, the redundancy circuit may be designed to include N fuse circuits 31_1 to 31_N.
Each of the first to Nth fuse circuits 31_1 to 31_N stores one bit of repair addresses RPR_ADDR<1:N>. The first to N fuse circuits 31_1 to 31_N will be described in detail in FIG. 2.
The column repair decision circuit 36 compares the repair addresses RPR_ADDR<1:N> received from the first to Nth fuse circuits 31_1 to 31_N with the column addresses ADDR<1:N> received from an external source. If the repair addresses RPR_ADDR<1:N> is same as the column addresses ADDR ADDR<1:N>, the column repair decision circuit 36 outputs a decision signal HIT having a high voltage level. If the repair addresses RPR_ADDR<1:N> is not same as the column addresses ADDR<1:N>, the column repair decision circuit 36 outputs a decision signal HIT having a low voltage level.
If the decision signal HIT has the low voltage level, an access operation is performed in a normal memory cell corresponding to the column addresses ADDR<1:N> received from the external source. If the decision signal HIT has the high voltage level, the access operation is performed in a redundant memory cell instead of the normal memory cell.
FIG. 2 is a detailed diagram illustrating a first fuse circuit shown in FIG. 1.
A first fuse circuit 31_1 includes a pre-charge unit 32, a first fuse unit 33_1, a second fuse unit 33_2, a transfer unit 35 and a latch unit 34.
The pre-charge unit 32 precharges a first node ND1 to a power supply voltage VDD in response to a pre-charge signal PCG_SIGB. The pre-charge signal PCG_SIGB is a signal which is deactivated from a low voltage level to a high voltage level when an active command is applied from an external source.
The first fuse unit 33_1 stores one bit of a first repair address for a column repair of a first cell mat (unit cell block). The first cell mat is activated in response to a first cell mat selection signal XMAT<1>. More specifically, the first fuse unit 33_1 establish a current path between a ground node VSS and a second node ND2 based on a state of a first fuse F1 when the first cell mat selection signal XMAT<1> is activated.
The second fuse unit 33_2 stores one bit of a second repair address for a column repair of a second cell mat. The second cell mat is activated in response to a second cell mat selection signal XMAT<2>. More specifically, the second fuse unit 33_2 establish a current path between a ground node VSS and a second node ND2 based on a state of a second fuse F2 when the second cell mat selection signal XMAT<2> is activated.
The transfer unit 35 couples the first node ND1 to the second node ND2 in response to an enable pulse signal EN_PUL. The enable pulse signal EN_PUL has a pulse width corresponding to a given period in response to the pre-charge signal PCG_SIGB.
If the first fuse circuit 31_1 is designed without the transfer unit 35, a malfunction of a fuse may occur due to a voltage difference between the first fuse F1 and the second fuse F2. For example, if the in first fuse F1 is in a cutting state and the first cell mat selection signal XMAT<1> of the first cell mat is activated after a voltage of the first node ND1 is pre-charged to the power supply voltage VDD by the pre-charge unit, a voltage of the first node ND1 is the power supply voltage VDD and a voltage of the second node is the ground voltage VSS because the current path is not established between the first node ND1 and the ground voltage VSS.
If the transfer unit 35 does not exist, the voltage difference is maintained between both ends of the first fuse F1. Thus, although the first fuse F1 is cut, the malfunction of the first fuse may occur. To resolve this concern, the transfer unit 35 is set and couples the first node ND1 to the second node ND2 during an activation period of the enable pulse signal EN_PUL.
The latch unit 34 latches a voltage of the first node ND1 and outputs a latched voltage as the first repair address RPR_ADDR<1>. When the first cell mat selection signal XMAT<1> is activated, the first repair address RPR_ADDR<1> indicates a lowest bit of a repair address for a column repair of the first cell mat. When the second cell mat selection signal XMAT<2> is activated, the first repair address RPR_ADDR<1> indicates a lowest bit of a repair addresses for a column repair of the second cell mat when the second cell mat selection signal XMAT<2> is activated.
FIG. 3 is a timing diagram illustrating an operation of the first fuse circuit 31_1 shown in FIG. 2.
The pre-charge signal PCG_SIGB is activated at a low voltage level during a pre-charge period T1 before an active command is applied. The pre-charge unit 32 precharges the first node ND1 to the power supply voltage VDD in response to the pre-charge signal having the low voltage level.
The pre-charge signal PCG_SIGB is shifted from a low voltage level to a high voltage level when the active command is applied from an external source. The enable pulse signal EN_PUL is activated at a high voltage level in response to the active command, and has an active width TA of a predetermined period.
The transfer unit 35 couples the first node ND1 to the second node ND2 in response to the enable pulse signal activated during the TA period.
As shown in FIG. 3, the first cell mat selection signal XMAT<1> is activated at a high voltage level and the second cell mat selection signal XMAT<2> is activated at a low voltage level. If the first fuse F1 is cut, the first node ND1 maintains a high voltage level because a current path is not established between the second node ND2 and the ground voltage VSS. If the first fuse F1 is not cut, a voltage of the first node ND1 is changed to a low voltage level, because a current path is established between the second node ND 2 and the ground voltage VSS.
After TA period, the enable pulse signal is deactivated at a low voltage level, and the first node ND1 is disconnected from the second node ND2. However a voltage level of the first node ND1 is maintained by the latch unit 34 during a second period T2. That is if the first fuse F1 is cut, the first node maintains a high voltage level during the second period T2, and if the first fuse F1 is not cut, the first node ND1 maintains a low voltage level during the second period T2.
The detailed description of the other fuse circuits 31_2 to 32_N is omitted since the other fuse circuits 31_2 to 32_N are similar to that of the first fuse circuit 31_1.
Furthermore, since an activation width of the enable pulse signal EN_PUL used in the first to Nth fuse circuits 31_1 to 31_N of a conventional redundancy circuit are determined by a delay circuit, the enable pulse signal EN_PUL has an influence on a process, voltage and temperature (PVT) variations.
For example, if a power supply voltage VDD having a high voltage level is supplied to a fuse circuit, the first node ND1 may be disconnected from the second node ND2 before the repair addresses RPR_ADDR<1:N> stored in the first to Nth fuse circuits 31_1 to 31_N are latched, because an activation width of the enable pulse signal EN_PUL is smaller than a predetermined width of the enable pulse signal EN_PUL. Thus, incorrect repair addresses RPR_ADDR<1:N> are output and may cause the malfunction of the redundancy circuit.